I swear this image feels older than me, anyone else still refer to this guy after years and years? I just feel uncomfortable using any other conversion chart.1yr ⋅ YoureHereForOthers ⋅ r/FPGA
When you don't remember if it's (others => '0') or (others <= '0') but kick off an autobuild anyway2yr ⋅ Employment-Deep ⋅ r/FPGA
When you spend months simulating a design and it works first try on hardware.2yr ⋅ Lekgolo167 ⋅ r/FPGA
Got me some programming socks! (one these in a drawing and apparently programming socks was a big meme about a month ago on programming humor)2yr ⋅ Lekgolo167 ⋅ r/FPGA
MAX1000 Webinar and you even get a free MAX1000 when you sign up (This will also address programming with the VHDPlus IDE)3yr ⋅ leonbeier ⋅ r/FPGA
My manager, who programmed once in university 20 years ago, after he discovered HLS3yr ⋅ fsasm ⋅ r/FPGA
Am I the only one doing scribbles like that? Helps me keep track of latencies, and stuff.1yr ⋅ shredEngineer ⋅ r/FPGA
Love it when the Xilinx Updater manages to completely spike a 5900x for twenty minutes straight2yr ⋅ heyspencerb ⋅ r/FPGA
A table illustrating how a D flip-flop is inferred through coding style.5mo ⋅ Hot_Respect_193 ⋅ r/FPGA
Does anyone know what FPGA NOCs support something called an “Fat H-Tree” Topology? (Basically, the closer any branch is to the exact center, the more resources and paths will be allocated to it, because paths closest to the center get the most traffic.)3yr ⋅ Vitalrnixofnutrients ⋅ r/FPGA
I couldn't find a simple diagram summarising the MAX1000 pinout. So I made one myself.3yr ⋅ Tabsels ⋅ r/FPGA
I’m being laid off soon, can you guys please take a look at my resume?2mo ⋅ Throwaway72728259 ⋅ r/FPGA
Just got my Varium C1100 as part of the 2021 Adaptive Computing Challenge, super excited to finally have it in my workstation. Thanks, Xilinx!2yr ⋅ TheSkyHighPolishGuy ⋅ r/FPGA
I bought this miniSpartan6+ in a Kickstarter in 2013. But at the time I moved to California and had to put it aside. I found it after 8 years and was all excited about my forgotten toy... only to discover the website is gone. Can somone help me get started developing with it or have the materials?2yr ⋅ ripred3 ⋅ r/FPGA
Looking for cool application ideas for my Bluetooth / iCE40 module (Crosspost-ish from /r/electronics)3yr ⋅ HammerFET ⋅ r/FPGA
I know it's old tech, but is any beginner interested in learning with one of these?3yr ⋅ raydude ⋅ r/FPGA
Does anyone know why this VHDL code is not counting on my FPGA? The 7-segment is stuck on 0. So I am assuming it is not making it to the second count for some reason.1yr ⋅ KingKato2014 ⋅ r/FPGA
2D DCT with Quantization followed by Dequantization and 2D IDCT amplifies noise a lot (e.g. green pixels). Any guesses what could be wrong?2yr ⋅ eg0lf ⋅ r/FPGA
I have recently purchased a xilinx VU9P based board. I'm a complete noob to vhdl and fpga, but I have extensive experience in c/c++. Do I need to purchase the vivado software or is there an opensource stack I can use?3yr ⋅ Psychological_Draw78 ⋅ r/FPGA
Is driving 3 LVDS Laptop LCDs from Single HDMI Input possible on an FPGA?1yr ⋅ braveduckgoose ⋅ r/FPGA
The conversation when explaining what the differential inputs on an FPGA mean is always magical3yr ⋅ dub_dub_11 ⋅ r/FPGA
Attention to everyone that is using Verilator and C++! DO NOT update your GCC Package to version 11.1, because it will cause Verilator's object files to fail to compile properly. I have been dealing with this issue for four days straight and have only now found the solution. You have been warned.3yr ⋅ vita1mixofnutrients ⋅ r/FPGA
cocotb: 2 orders of magnitude simulation speedup after switching from icarus to verilator (fixed recently). Wow.1yr ⋅ minus_28_and_falling ⋅ r/FPGA
Got this $38 TinyFPGA BX after searching for a cheap and newbie friendly FPGA. Highly recommended!4yr ⋅ nerdOnline ⋅ r/FPGA
What’s the best tool for OS X to synthesize a circuit like this, this example says it was done with synplify premier?1yr ⋅ BillyWayneSmith ⋅ r/FPGA
Lattice Diamond support added to the PipelineC compiler. Can you pipeline logic better than a tool? Take the pipeline challenge!3yr ⋅ absurdfatalism ⋅ r/FPGA
Do you like HLS II=1 pipelining in C code but also want regular HDL clock by clock control too? Do you use Xilinx, Intel, Lattice, or Efinix(NEW!) FPGAs? PipelineC might be for you.2yr ⋅ absurdfatalism ⋅ r/FPGA
Compiling error with GHDL, but it works fine with Quartus or ModelSim. Im trying to concatenate a constant with other constants: LDI & R3 & 0011, when i try to compile with GHDL using Vunit I get the following error on that line: type of element is ambiguous. DO you guys have any clue?1yr ⋅ turbobondenn ⋅ r/FPGA
I made a circuit that counts the one bits in an eight bit unsigned number. WooHoo!4yr ⋅ superrenzo64 ⋅ r/FPGA
The 8 Stages of FPGA Development is a bubble diagram I created a few years ago when I realized this job has common stages that I feel and experience while working a design. Maybe you can relate? We never leave Stage 8!4yr ⋅ DigitalKrampus ⋅ r/FPGA
